This invention pertains generally to the field of cardiac pacemakers and implantable cardioverter/defibrillators incorporating a pacing function. In particular, the invention relates to the hardware and software used to control the operation of such devices.
Most cardiac pacemakers today (including implantable cardioverter/defibrillators with pacing capability) are microprocessor-based systems in which software run by the microprocessor commands the generation of pacing outputs, with various timers being used to alert the microprocessor as to when to pace. Such microprocessor-based systems exhibit great flexibility, as compared with a pacemaker implemented with dedicated hardware, since the operation of the device can be changed simply by reprogramming the microprocessor. Controlling the operation of a pacemaker totally with a microprocessor-based system, however, also has some disadvantages. If the microprocessor continually executes instructions during the cardiac cycle in order to process and respond to timing and sensing events, a large amount of battery power is consumed. Also, making pacing decisions with software inevitably introduces some variability into the timing of the paces, commonly referred to as xe2x80x9cpacing jitter.xe2x80x9d
The present invention is embodied by a pacemaker that employs a hybrid microprocessor-based and hardware-based system to control its operation. In an exemplary embodiment, the pacemaker may be configured to pace in any of a number of different pacing modes, including biventricular pacing modes. In accordance with the invention, a plurality of hardware timers define particular timing intervals to which the pacemaker responds. For each timer, a compare register writable by a microprocessor-based controller is used to store a specified limit value for the timer, and a comparator generates a timer expiration signal for each timer when the output of the timer equals the limit value. The microprocessor can update the limit values of each compare register between cardiac cycles as defined by the expiration of a particular timer. Sensing channels may be provided for an atrium and/or ventricle, which sensing channels include a sense amplifier for amplifying a voltage from an electrode in electrical contact with a heart chamber and thereby detecting depolarizations occurring in the heart chamber. Ventricular and/or atrial stimulus generators are provided for generating paces by outputting pacing voltage pulses to electrodes in contact with the heart chamber to be paced. A combinational logic array interprets detected depolarization signals in order to generate sensing signals and triggers the stimulus generator in response to the expiration of particular timers and the generation of particular sense signals in accordance with a programmed pacing mode. A mode control register writable by the microprocessor contains a mode value stored by the microprocessor-based controller such that the combinational logic array enables or disables certain timers so as to cause the pacemaker to operate in a particular pacing mode in accordance with the mode value.